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[VHDL-FPGA-Verilog] Viterbidecoder

Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Platform: | Size: 386048 | Author: 杨艺 | Hits:

[Other] rs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 133120 | Author: yuanfeng | Hits:

[VHDL-FPGA-Verilog] Cpu_model

Description: Verilog HDL编写的CPU模型，很经典，比较通用-Verilog HDL prepared by the CPU model, classic, more generic
Platform: | Size: 1024 | Author: wyl | Hits:

[ELanguage] rs-codec-8-4

Description: encode.v The encoder syndrome.v Syndrome generator in decoder berlekamp.v Berlekamp algorithm in decoder chien-search.v Chien search and Forney algorithm in decoder decode.v The top module of the decoder inverse.v Computes multiplication inverse of an Galois field element test-bench.v The test fixture, and some brief notes on using the modules. data-rom.v A simple data source for testing run For those intelligence-challenged who can t run verilog LGPL The license -encode.v syndrome.v Syndrome generator in decoder al berlekamp.v Berlekamp gorithm in decoder chien- search.v Chien searc h and Forney in decoder algorithm decode.v The t op module of the decoder inverse.v Computes intercommunication tiplication inverse of an element over Galois field test-bench.v The test fixture. and some brief notes on using the modules. data- rom.v A simple data source for testing run For th PNA intelligence-challenged who can not run veri The log LGPL license
Platform: | Size: 45056 | Author: zs8292 | Hits:

[Special Effects] djpeg_vlsi

Description: jpeg解码电路，是verilog编写的，可以综合，很有实用价值。-jpeg decoder circuit, is prepared verilog, synthesis, very practical value.
Platform: | Size: 181248 | Author: blueli | Hits:

[Embeded-SCM Develop] viterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44032 | Author: 林四昆 | Hits:

[VHDL-FPGA-Verilog] mancheester_v

Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Platform: | Size: 9216 | Author: wangyunshann | Hits:

[SCM] Source

Description: PS2键盘实验源代码，Verilog语言编写-PS2 keyboard experiment source code, Verilog language
Platform: | Size: 3072 | Author: zhan | Hits:

[VHDL-FPGA-Verilog] RS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[Special Effects] JPEGDecoder

Description: JPEG解码器的硬件语言描述，主要的描述语言是verilog,用硬件结构实现了解码功能。-JPEG decoder hardware description language, the main language is described in verilog, with hardware structure realize the decoding capabilities.
Platform: | Size: 199680 | Author: liusu | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
Platform: | Size: 113664 | Author: 张席龙 | Hits:

[VHDL-FPGA-Verilog] c23_RS_decoder

Description: 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
Platform: | Size: 13312 | Author: 李平 | Hits:

[Communication-Mobile] decoder

Description: 用verilog编写的bch译码器，包括测试文件，随机加载了比特流，进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
Platform: | Size: 357376 | Author: 牛顿 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[Compress-Decompress algrithms] H.264

Description: H.264标准解码器全部verilog源码，包括帧内、帧间、变换编码、熵编码、滤波等所有模块-Standard H.264 decoder all verilog source, including intra-, inter-frame, transform coding, entropy coding, filtering all modules
Platform: | Size: 827392 | Author: liu | Hits:

[VHDL-FPGA-Verilog] decoder

Description: 一个verilog源代码，用于译码器的编程。-A verilog source code, for programming decoder.
Platform: | Size: 65536 | Author: PUDN_CHEN | Hits:

[VHDL-FPGA-Verilog] ldpc_decoder_802_3an_latest.tar

Description: 802.3an ldpc decoder verilog 源码
Platform: | Size: 884736 | Author: 杨振飞 | Hits:

[VHDL-FPGA-Verilog] rs_decoder204_188

Description: RS译码的Verilog实现，用的是改进的BM算法，已在QuautusII9.0上调试通过-rs decoder verilog
Platform: | Size: 9468928 | Author: songbing | Hits:

[VHDL-FPGA-Verilog] LIP6431CORE_NTSC_Video_Decoder

Description: NTSC Video Decoder Verilog Source code
Platform: | Size: 1537024 | Author: jc | Hits:

[Compress-Decompress algrithms] Huffman-Decoder-master

Description: 用verilog编写的huffman解码程序(huffman decoder verilog)
Platform: | Size: 4096 | Author: 张巨炮 | Hits:
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